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FRED E. WAHL > resume

OBJECTIVE
Re-enter silcon valley work market in a fully-employed fashion. As Project Contributor, Lead or Supervisor.
On projects requiring a large Scientific, Engineering and IT knowlege base.

SUMMARY
Educated through MSEE level with IC industry experience starting in 1972. Recent focus in
Characterization and Spice Modeling of CMOS devices. Recent certificate in IC Digital Design.
Work history includes technical, engineering and supervisorial positions in Process R&D,
Yield Engineering, CMOS Technology qualification, Design Support, Physical Design of
testchips and programming of test systems. Spice Model parameter extraction done using
BSIM3v3 down to 0.13um CMOS. Chip / Device measurements and analysis to assist Design,
Product and Reliability groups. Assisted development of Interconnect Parasitics extraction
flow for Cirrus Logic. While at Altera did 65 nm CMOS Scribeline layout, Test Development
and execution using Agilent SPECS. Recent instruction: SVTI "ESD Design for Mixed Signal
and RF Applications" February 2008, “Design-for-Yield/Design- for-Mfg Trends” July 2006,
at Cadence “Virtuoso Layout & XL Layout Editor” classes in March 2006.

TECHNICAL SKILLS
Scientific / Engineering: Physics, Math, Statistics and EE training. Semiconductor device physics and
parameters, Device measurements, Test chip design and layout. Electronics testing, Circuit simulation,
some CAD and TCAD tools, Test hardware acquisition, system integration, programming, maintenance and use.
Tools: Ledit, Pdracula, BSIMpro, BSIM-ET, Hspice, Smartspice, Arcadia, MatLab, Cornerstone, SPECS,
HTBASIC, some LabView, VERILOG, Synopsys Design Compiler, Cadence Virtuoso & XL Layout Editors
Informational: Design of relational and web-based databases, Web page design and maintenance.
Tools: Informix, SQL, Sybase PowerBuilder, Cute FTP, Dreamweaver, Frontpage, IEEE Xplore
Computers / Programming: Sun/PC hardware and software, Ethernet, Backups, Unix, Linux,
Microsoft Windows. Languages: BASIC, Visual Basic, C, C++, shell script, PERL, Latex, Emacs, Assembly
Office Tools: Adobe Acrobat, Distiller, Photoshop, Excel, Word, PowerPoint, Project

EXPERIENCE
ABOVEBOARDELECTRONICS, San Jose CA   (Mar 2008 -- Present)
ALTERA, San Jose CA                (Aug 2005 – Jan 2006)
Device Engineer position in CMOS Technology Modeling and Characterization department at Altera.
Use of TEL 12”auto wafer prober, Agilent SPECS test system. FET, Ring Oscillator and CBCM measurements.
Group technical information web page maintenance.
VOLUNTEER WORK with FSA (Fabless Semiconductor Association)      (July 2004 – Aug 2005)
Assisting MS/RF/HV Spice Model Standards team, led by Ken Brock of Silvaco and Pekka Ojala of EXAR.
CIRRUS LOGIC INC, Fremont CA 1991-March 2003
MANAGER, Technology Characterization (2001-March 2003)
Maintained Technology Characterization service as group function transferred to new corporate
headquarters in Austin, Texas. Assisted transfer and training of personnel.
*Developed an economical characterization system using E5250A, and HP4156B
*Coordinated test chip test and modeling project at CSM Foundry onsite in Singapore
*Assisted transfer of “Design Kit” and methods to Texas
*Insured success of new database and fed it historic data from previous database
MANAGER Characterization, Design Infrastructure (1999-2001)
Assisted group project to create and maintain web-based information system called “Design Kit” to
provide CAD tool, process design, and char information critical to Circuit Design group.
Supported Design, Product, and Fab engineering requested characterizations. Provided continuing
development and maintenance of client-server database.
*Wrote Spice Modeling Specification to help guarantee ‘first time success’ designs
*Assisted content choice and test of Unix automated Foundry Spice Model QA method
MANAGER, Characterization and Modeling (1998-1999)
Provided Spice Model Development and Quality Assurance. Used BSIMpro to develop corporate
BSIM Spice Models. Capacitance-voltage measurements used to create model capacitance
parameters. Calibrated models to silicon using Ring Oscillator simulations and measured gate delay.
*Spice accuracy improved using back-annotated netlist interconnect parasitic calculation
*Promoted database use resulting in happy users at Fremont, Austin and Colorado sites
SECTION MANAGER, Characterization (1994-1998)
Manage and train Characterization section reporting to Director of Technology Qualification.
Projects: Electrical Design Rules development and test, Test chip design and layout, Parametric
testing, Characterization, Interconnect parasitics tool evaluation, TLP snapback test, and Wafer
Level Reliability methods development.
*Specified and brought up second HP4062 for advanced Technology testing
*Led project to create Engineering client-server database from Informix and PowerBuilder
*Developed Pelgrom field-effect FET mismatch methods, results used by design
ENGINEER, Etest and Characterization (1992-1994)
Created Characterization Lab and acquired needed test equipment. Developed Process and Device Characterization/Technology Analysis Reports. Performed wafer split lot analyses for Yield check.
Led system requirements definition and prototyped engineering databases for Yield Monitoring.
*Produced, edited Training Videos for Etest operators and technicians consistent with spec
*Wrote Etest specifications for operations, test maintenance and engineering
*Designed and contracted building of an Electromagnetic shield box for lab prober
SENIOR DEVICE ENGINEER (1991-1992)
Set up corporate Etest/Process Control Monitor capability using HP4062 test system and Electroglas
automatic wafer prober. Device measurements to support yield improvement. Standardized parameters
and test definitions. Developed lot parameter Pass/Fail reports for wafer and lot acceptance (WAT).
*Developed test system software design which served the company for the next 10 years
TECHNOLOGY MODELING ASSOCIATES, Palo Alto CA 1990-1990
SENIOR MEMBER, Technical Staff
Continued development of Unix Spice Modeling software TOPEX. Assisted attempt to migrate to PC
*Produced one full new release and one beta release and several application notes
*Presented slide show on TOPEX with BSIM at TMA TechMart annual customer show
OTHER RELATED EMPLOYMENT
SIGNETICS/PRLS (Philips Research Labs Sunnyvale), Sunnyvale CA. Developed Wafer Contour
Mapping System to study process uniformity. BiCMOS process development team member.
Spice/SLIC Modeling. Bipolar Mem Yield Engr. Wafer Sort Engr. Ion Implant process qualification.
10-bit D/A development. Spreading Resistance doping profiling. Implant/thin film QA tool design.

EDUCATION
*Certificate, VLSI Design Engineering, University of California Extension, Santa Cruz
*MSEE, University of Santa Clara, Santa Clara, CA. Semiconductor Emph. & Analog & Digital Des
*BS Physics / 2nd Major Applied Math, San Jose State University, San Jose, CA
*Technical coursework for AS Electronics, Foothill Community College, Los Altos CA

PROFESSIONAL DEVELOPMENT
*Compact MOSFET Models & TCAD Methodology..,SVTII instr Samar Saha (June 2006)
*Cadence Virtuoso Layout Editor and XL Layout Editor, Cadence instr Jerry Clark (Mar 2006)
*Certificate in “VLSI Design Engineering”, UCSC extension (Sep 2005)
*Wafer Level Reliability, UCSC extension instr Dr Sunil Shabde (April 2005)
*Transistor and Interconnect Models from Foundries, UCSC ext inst Dr. Asim Hussain (2005)
*Digital Design using VERILOG, UCSC ext, instructor Charles Dancak (Aug 2004)
*CMOS Analog Integrated Circuits, Georgia Tech, instructor Dr. Phillip E. Allen (2004)
*Developing Engr Appls with MS Visual C++ Devel Studio, instructor Dr. James McDonald(2004)
*Intro to VLSI and ASIC Design, UCSC ext, instrs Mukesh Amlani and Suresh Honnenahalli(2004).
*Analog Design for Digital Designers, Cirrus (2001)
*FSA sponsored Spice and Interconnect Modeling Workshops (2002 and 2000)
*High Speed Circuit Design for Digital Designers,Cirrus (1999)
*Using BSIMpro to extract BSIM CMOS parameters, BTA (1999)
*MOS Devices: Physics, Technology, Reliability, Modeling and Characterization,
    UC Berkeley Ext (1998)
*Semiconductor Process and Device Characterization, Ariz State Univ (1997)
*Relational Database Design, Structured Query Language, etc., Informix (1994)
*Design for Manufacturability, Cirrus (1993)